Floating gate cells are used for many non-volatile memory (NVM) systems. A floating-gate NVM cell typically includes a source region, a drain region, a floating gate, and a control gate positioned above the floating gate. Wordlines for rows of floating-gate NVM cells are formed using control gate layers. During operation, charge is added to or removed from the floating gate to determine its logic state. To reduce the size of floating-gate NVM cell arrays, it is desirable to reduce the feature sizes for the floating gates for the floating-gate cells.
FIG. 1 (Prior Art) is a top view diagram of an example embodiment 100 for a floating gate cell area. A drain contact 104 has been formed within a drain region 102, and a source contact 108 has been formed within a source region 106. A floating gate 114 is positioned between the source region 106 and the drain region 102 underneath the control gate (CG) layer, only portions 112 for which are shown. For the embodiment 100 depicted, the floating gate 114 includes wing portions 120 that extend over STI (shallow trench isolation) regions 110 that are positioned adjacent the edges of the floating gate, source region 106, and drain region 102. The floating gate area is defined in part by the area represented by a product of the channel length (L) 116 and the channel width (W) 118 plus the wing portions 120. Shrinking of these floating gate dimensions is desirable to reduce the size of the overall cell array
FIG. 2 (Prior Art) is a cross-section view diagram of an embodiment 200 along dashed line 122 in FIG. 1 (Prior Art). A doped well region 202 has been formed within a semiconductor substrate along with STI regions 110. A gate oxide 210 is positioned above the well region 202, and a floating gate (FG) 114 has been formed over the gate oxide 210. The floating gate layer used to form the floating gate 114 is typically deposited and then patterned using a lithography tool to form slits on either side of the floating gate. The dimensions 212 for these floating gate slits, therefore, are dependent upon the lithographic dimensions allowed by the tool. A dielectric layer 208, such as an oxide layer, is formed over the floating gate 114 and the STI regions 110. A control gate (CG) layer 112 is then formed over the dielectric layer 208. Although not shown, additional well regions and floating gates would be positioned on either side of the floating gate (FG) 114 and well region 202 if an array of floating-gate NVM cells were being formed during manufacture.
As can be seen, if dimensions for the floating gate 114 are reduced, the control gate layer 112 within the floating gate slits is also moved closer to the doped well region 202. This reduced distance between the control gate layer 112 and the doped well region 202 within the floating gate slits may lead to lower breakdown voltages within regions 220 and 222. This reduced breakdown voltage can in turn cause performance degradations and reduced reliability for resulting floating-gate NVM cell arrays. Prior solutions attempt to reduce this breakdown risk by forming control gate and/or floating gate structures that require the use of higher resolution lithography tools that allow reduced feature sizes. These higher resolution lithography tools, however, add undesirable complexity and cost to the manufacturing process.